111: Kay Li

Date: 2024-05-08

Duration: 01:18:12

Kay Li joins to talk about custom hardware used in high-frequency trading, development workflows for FPGA and ASIC design, and why verification has become a bottleneck in the design process. We also discuss SiLogy, the startup Kay founded with Paul Kim to improve the design workflow, including their experience applying to and going through YCombinator, their initial target market, and how the platform could evolve over time.

Kay on LinkedIn: https://www.linkedin.com/in/kay-li-84924128b/

Kay on Twitter: https://twitter.com/silikayli

Show Notes

Welcome Kay (00:02:07)
Kay’s Introduction to Computing (00:02:57)
Learning Programming with FORTRAN (00:03:29)
- https://en.wikipedia.org/wiki/Fortran
Focus on Mathematics (00:04:02)
First Computer (00:04:14)
Intel Pentium III (00:04:22)
- https://en.wikipedia.org/wiki/Pentium_III
Exposure to Computer Science in Northwest Florida (00:05:06)
Math Competitions (00:05:49)
Math Classes at University of West Florida (00:06:03)
- https://uwf.edu/
Attending University of Chicago (00:06:56)
- https://www.uchicago.edu/
Realizing Career Wouldn’t be as Mathematician (00:07:25)
Family Background in Academia (00:08:31)
László Babai (00:09:19)
- https://en.wikipedia.org/wiki/L%C3%A1szl%C3%B3_Babai
Functional Programming (00:09:47)
- https://en.wikipedia.org/wiki/Functional_programming
Elm Language (00:09:49)
- https://elm-lang.org/
Matt Godbolt on the Microarch Club (00:10:01)
- https://microarch.club/episodes/101/
Getting into Financial Trading (00:10:20)
Chicago Mercantile Exchange (CME) (00:10:48)
- https://en.wikipedia.org/wiki/Chicago_Mercantile_Exchange
University of Chicago Booth School (00:11:07)
- https://www.chicagobooth.edu/
Eric Budish (00:11:11)
- https://www.chicagobooth.edu/faculty/directory/b/eric-budish
The High-Frequency Trading Arms Race (00:11:22)
- https://papers.ssrn.com/sol3/papers.cfm?abstract_id=2388265
Flash Boys (00:11:41)
- https://en.wikipedia.org/wiki/Flash_Boys
The Value of High-Frequency Trading (00:11:59)
Joining a Trading Firm (00:12:55)
Life as a Quant (00:13:34)
FPGAs in High-Frequency Trading (00:14:26)
- https://en.wikipedia.org/wiki/Field-programmable_gate_array
The Prevalence of Custom Hardware in High-Frequency Trading (00:14:58)
Previous Exposure to FPGAs (00:15:41)
Benefits of Working at a Small Firm (00:16:36)
First FPGA Programs (00:17:01)
CME Market Data Platform (MDP) FIX Message Format (00:17:16)
- https://www.cmegroup.com/confluence/display/EPICSANDBOX/MDP+3.0+-+Message+Specification
Trigger-Based Trading (00:17:41)
- https://www.fidelity.com/learning-center/trading-investing/trading/conditional-order-types
Frequency of Reprogramming FPGAs (00:18:14)
HDLs Used in High-Frequency Trading (00:19:02)
- https://en.wikipedia.org/wiki/Hardware_description_language
Verilog (00:19:11)
- https://en.wikipedia.org/wiki/Verilog
Design Verification (00:19:16)
- https://www.chipverify.com/tutorials/verification
How Verification Works (00:19:49)
- https://verificationacademy.com/topics/fpga-verification/
Parallelism of Hardware (00:20:23)
Pre-Synthesis Verification (00:20:56)
RTL Testbenches (00:22:33)
- https://www.chipverify.com/verilog/verilog-testbench
Constrained Randomization (00:23:08)
- https://vlsiverify.com/system-verilog/randomization-in-systemverilog/
Optimization in FGPA Design (00:23:44)
- https://web.eecs.utk.edu/~dbouldin/protected/fpga-optimizations.pdf
When FPGAs Aren’t Enough (00:25:18)
Prevalence of ASICs in Trading (00:25:43)
Joining Hudson River Trading (HRT) (00:26:18)
- https://www.hudsonrivertrading.com/
Open Source at HRT (00:27:11)
- https://github.com/hudson-trading
FPGA Design Tooling (00:27:28)
Verilator (00:28:02)
- https://www.veripool.org/verilator/
cocotb (00:28:04)
- https://www.cocotb.org/
Todd Strader (00:28:28)
- https://www.linkedin.com/in/todd-strader-10b08a15/
How We Verify Custom Hardware at HRT (00:28:35)
- https://www.hudsonrivertrading.com/hrtbeat/verify-custom-hardware/
Limitations of Open Source Tooling (00:28:39)
Cycle-Based vs. Event-Based Simulators (00:29:41)
- https://www.asic-world.com/verilog/verifaq3.html
Encrypted IP (00:30:23)
- https://www.intel.com/content/www/us/en/docs/oneapi/programming-guide/2023-2/encrypt-ip-components-for-distribution.html
2-State vs. 4-State Data Types (00:30:47)
- https://www.chipverify.com/systemverilog/systemverilog-data-types-logic-bit
Post-Synthesis Verification (00:31:36)
- https://docs.amd.com/r/en-US/ug900-vivado-logic-simulation/Post-Synthesis-Simulation
Parallelism in FPGA Verification (00:32:01)
Use of IP Blocks in Logic Design (00:33:04)
- https://en.wikipedia.org/wiki/Semiconductor_intellectual_property_core
Debuggability of Proprietary IP Blocks (00:34:45)
Process for Purchasing IP Blocks (00:35:35)
Decision to Leave Hudson River Trading (00:36:24)
Waiting Out a Noncompete (00:37:07)
Prevalence of Noncompetes in Trading (00:38:00)
- https://www.ftc.gov/news-events/news/press-releases/2024/04/ftc-announces-rule-banning-noncompetes
Learning Rust (00:39:48)
- https://www.rust-lang.org/
Decision to Start a Company (00:40:14)
Making It Easier to Get Started with FPGAs (00:41:46)
Pain Points in FPGA Development (00:42:16)
Rising Complexity in Chip Design (00:43:31)
Project Euler (00:44:05)
- https://projecteuler.net/
Decision to Do YCombinator (00:45:17)
- https://www.ycombinator.com/
Place & Route (00:46:45)
- https://en.wikipedia.org/wiki/Place_and_route
Finding a Co-founder (00:47:12)
Paul Kim (00:47:28)
- https://www.linkedin.com/in/paul-kim-7b766262/
Cloudflare Auth Service (00:47:29)
CEO vs. CTO Role (00:48:54)
YCombinator Application Process (00:50:44)
Brad Flora (00:52:09)
- https://www.ycombinator.com/people/brad-flora
Launching SiLogy (00:52:31)
- https://silogy.io/
- https://news.ycombinator.com/item?id=39632872
Framer (00:53:38)
- https://www.framer.com/
James, SiLogy Founding Engineer (00:53:51)
- https://www.linkedin.com/in/james-c-16334ba4/
Naming the Company (00:54:08)
Why Focus on Verification? (00:55:22)
Asianometry Video on the Verification Gap (00:56:03)
- https://www.asianometry.com/p/the-growing-semiconductor-design
Outsourcing of Verification (00:57:28)
Impact of Rising Software Engineering Salaries on Chip Design (00:58:58)
NVIDIA Design Verification Workflow (01:00:12)
Bottlenecks in Verification (01:00:56)
Collaboration in Design Verification (01:01:17)
Currently Supported Tooling on SiLogy (01:03:07)
GitHub Applications (01:03:45)
- https://docs.github.com/en/apps/creating-github-apps/about-creating-github-apps/about-creating-github-apps
Comparing SiLogy to General Purpose CI Services (01:04:23)
Early Target Market for SiLogy (01:05:43)
Working with Other Startups (01:06:17)
Tiny Tapeout (01:06:43)
- https://tinytapeout.com/
Open Source Process Development Kits (PDK) (01:06:46)
- https://www.skywatertechnology.com/sky130-open-source-pdk/
FOSSI LatchUp (01:06:53)
- https://fossi-foundation.org/latch-up/2024
Expanding into Other Parts of Chip Design Workflow (01:07:27)
Possibility of Developing New Tooling (01:08:37)
An IP Block Marketplace (01:10:32)
How to Try SiLogy Today (01:12:54)
- https://calendly.com/d/5gd-rf6-66h/demo?month=2024-05
The Impact of AI Workloads on Microarchitecture (01:13:59)
CUDA and the Importance of a Software Ecosystem (01:15:40)
- https://en.wikipedia.org/wiki/CUDA

Transcript

Coming soon.